Re: Display Port support in RunBMC


Wszolek, Kasper
 

Hi Eric,

 

Thank you for providing the options below. First option (VGA pins reuse) is more preferable in my opinion and it’s exactly how I pictured adding DP support to RunBMC.

 

Here are some comments on both options:

  • It looks like the backward compatibility will be broken for both options. HW straps (as you indicated below) will be needed to maintain compatibility between different implementations on HW-level (if compatibility is required for particular design).
  • VGA vs. DP is more of a system design choice: it goes with video output standard choice and different electrical requirements for the main board as well, video connector options etc. In my opinion from RunBMC perspective it’s very similar case as with 1GbE PHY options – it’s not possible to support both 1GbE PHY configurations at the time with current version of the spec as well (without HW changes).
  • With second option (GPIO only) more GPIOs will be repurposed to DP than when reusing VGA pins.
  • DC-SCM example designs go with DP. DP connectors are much smaller and easier to integrate on front panel. I think that we can expect more adoptions of DP vs. VGA in the future due to size constrains and VGA availability on the displays.

 

Can we schedule to discuss this topic on one of sub-project meeting you are planning to set up?

 

--

Thanks,

Kasper

 

 

From: Eric Shobe <eric.shobe@...>
Sent: Tuesday, December 1, 2020 23:34
To: Wszolek, Kasper <kasper.wszolek@...>; OCP-HWMgt-Module@OCP-All.groups.io
Cc: Jared Mednick <jared.mednick@...>; Eric Shobe <shobe@...>; Jared Mednick <jaredm@...>
Subject: Re: Display Port support in RunBMC

 

Hi Kasper, 

 

I cc'ed the alias for OCP HW Mgmt. 

To support Display Port here are the changes.  

 

Pins

Requester

High Level Changes

DPAUXP
DPAUXN
DPTXP0
DPTXN0
DPHPD
DPTXP1
DPTXN1

Intel

1. Add filtering for TX pairs
2. Add HW straps on daughter board to support dual function for TX pairs
3. Add HW straps for AUX diff pair
4. Add HW strap HPD presence
5. Describe filtering/circuitry needed near DP connector on mobo
6. Can't share all on VGA because block already has dual function and backward compat would be lost. However we could use DACR/G/B and partial GPIO block OR all GPIO block

 

Looking at the possible pin-out changes: 

 

Pinout to share VGA block.  We would loose backward compat with 4 GPIO signals

DACG_DPAUXP

10

DACB_DPAUXN

12

DACR_DPHPD

14

VGAHS_GPIO2DPTXPO

16

VGAVS_GPIO4DPTXNO

18

DDCCLK_GPIO6DPTXP1

20

DDCDAT_GPIO8DPTXN1

22

 

 

Pintout to share GPIO block. Would need to add HW multiplex via resistor straps and filtering. 

 

GPIO19_DPAUXP

36

GPIO20_DPAUXN

38

....

GPIO38_DPHPD

66

GPIO39_DPTXP0

68

GPIO40_DPTXN0

70

GPIO42_DPTXP1

72

GPIO44_DPTXN1

74

 

 

Which one seems preferable from your side?

 

Eric

 

On Sat, Nov 28, 2020 at 1:44 PM Wszolek, Kasper <kasper.wszolek@...> wrote:

Hi Eric and Jared,

 

Hope you guys are doing great. I’ve enjoyed your presentation on OCP TECH WEEK – thank you for nice words about our RunBMC module and the demo 😊 I just want to let you know that we are still working internally on the process to eventually contribute our RunBMC module design to OCP. We’re bringing up the second version of the module now with some additional fixes we did based on the first version we showed on the demo.

 

I noted down your objectives to be addresses in the next version of the spec but I don’t recall that you mentioned Display Port support option in new spec version? I’m wondering if you explored it already? We are looking for a way to support that with RunBMC and it seems that from RunBMC pins perspective the VGA pins could be reused for Display Port assuming 2 Lanes, Aux Lane and presence detect there are exactly 7 pins needed. I’d assume it would have to be the similar option as you defined for 1GbE PHY solution i.e. either VGA or DP made as design decision. I’m wondering what’s you vision for that. I can also start this thread in management module discussion if you’d like to keep it there.

 

--

Thanks,

Kasper

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Intel Technology Poland sp. z o.o.
ul. Słowackiego 173 | 80-298 Gdańsk | Sąd Rejonowy Gdańsk Północ | VII Wydział Gospodarczy Krajowego Rejestru Sądowego - KRS 101882 | NIP 957-07-52-316 | Kapitał zakładowy 200.000 PLN.
Ta wiadomość wraz z załącznikami jest przeznaczona dla określonego adresata i może zawierać informacje poufne. W razie przypadkowego otrzymania tej wiadomości, prosimy o powiadomienie nadawcy oraz trwałe jej usunięcie; jakiekolwiek przeglądanie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by others is strictly prohibited.

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