RunBMC v1.5 Change RFC


Eric Shobe
 


Hi all,

I want to welcome everyone to comment on the following proposed changes for RunBMC v1.5. 
The change requests we have received so far are the following:

  •  Add Display Port Functionality [need to decide]

From RunBMC pins perspective the VGA pins could be reused for Display Port assuming 2 Lanes, Aux Lane and presence detect there are exactly 7 pins needed. 
The following high level changes would be needed to support this. 

1. Add filtering for TX pairs 
2. Add HW straps on daughter board to support dual function for TX pairs
3. Add HW straps for AUX diff pair
4. Add HW strap HPD presence
5. Describe filtering/circuitry needed near DP connector on mobo

The pinout proposal is here. 

  • eMMC functionality [proposed]
If the specification was to be changed to say "eMMC may be added on the RunBMC module", we don't see that as changing anything.  Today, with the specification, anyone who wants to design a RunBMC module can choose to add eMMC or not.
If designs add eMMC over the connector some will loose 4 pairs of I2C pins (I2C10 to I2C13).
  • BMC SD interface. Add SD interface
Screen Shot 2021-01-24 at 9.43.18 PM.png

  • Add PWRGB signal. [proposed]

We will add pin95(GPIO63) to be BMC_PWRGD(output)

95 BMC_PWRGD_GPIO63  
 
  • Add PFR Reset Signal [proposed]
We will add one more reset input pin on pin93(GPIO61) as PFR_RST#

93 PFR_RST#_GPIO61 

CPLD/circuitry can use the signal to let BMC in reset state.

  • Change pin name from CPU_RST# to PLT_RST# [proposed]

  • I3C [proposed]
Add the I3C3-6 pin definition below. (The I3C 1.0/1.2V signals
need to co-lay with following GF pins.) If user need the I3C 1.0V/1.2V function, please add
a level shift logic IC at MB side.

Screen Shot 2021-01-24 at 9.57.28 PM.png

Thanks,
Eric


Lior Elbaz
 

Hi Eric,

 

Can you elaborate on PFR_RST# signal and what is the different between current BMC_RESET# pin 253 ?

BMC_RESET#  also keep BMC in reset (core reset).

 

what is the usage of BMC_PWRGD(output) ? is it from RunBMC to MB signal ?

Note that currently there is PWRGD signal pin 77 from MB to RunBMC.

 

Can you elaborate on PLT_RST# signal ? is it BMC power-on-reset signal ?

Note that Nuvoton model currently support it on pin 95.

 

Regards,

Lior.

 

From: OCP-HWMgt-Module@OCP-All.groups.io <OCP-HWMgt-Module@OCP-All.groups.io> On Behalf Of Eric Shobe via groups.io
Sent: Monday, January 25, 2021 08:02
To: OCP-HWMgt-Module@OCP-All.groups.io
Subject: [OCP-HWMgt-Module] RunBMC v1.5 Change RFC

 


Hi all,

 

I want to welcome everyone to comment on the following proposed changes for RunBMC v1.5. 

The change requests we have received so far are the following:

 

  •  Add Display Port Functionality [need to decide]

 

From RunBMC pins perspective the VGA pins could be reused for Display Port assuming 2 Lanes, Aux Lane and presence detect there are exactly 7 pins needed. 

The following high level changes would be needed to support this. 

 

1. Add filtering for TX pairs 

2. Add HW straps on daughter board to support dual function for TX pairs
3. Add HW straps for AUX diff pair
4. Add HW strap HPD presence
5. Describe filtering/circuitry needed near DP connector on mobo

 

The pinout proposal is here. 

 

  • eMMC functionality [proposed]

If the specification was to be changed to say "eMMC may be added on the RunBMC module", we don't see that as changing anything.  Today, with the specification, anyone who wants to design a RunBMC module can choose to add eMMC or not.

If designs add eMMC over the connector some will loose 4 pairs of I2C pins (I2C10 to I2C13).

  • BMC SD interface. Add SD interface

Screen Shot 2021-01-24 at 9.43.18 PM.png

 

  • Add PWRGB signal. [proposed]

We will add pin95(GPIO63) to be BMC_PWRGD(output)

 

95 BMC_PWRGD_GPIO63  

 

  • Add PFR Reset Signal [proposed]

We will add one more reset input pin on pin93(GPIO61) as PFR_RST#

93 PFR_RST#_GPIO61 

CPLD/circuitry can use the signal to let BMC in reset state.

  • Change pin name from CPU_RST# to PLT_RST# [proposed]
  • I3C [proposed]

Add the I3C3-6 pin definition below. (The I3C 1.0/1.2V signals
need to co-lay with following GF pins.) If user need the I3C 1.0V/1.2V function, please add
a level shift logic IC at MB side.

 

Screen Shot 2021-01-24 at 9.57.28 PM.png

 

Thanks,

Eric


The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton.


Eric Shobe
 



On Mon, Jan 25, 2021 at 7:44 AM Lior Elbaz <lior.albaz@...> wrote:

Hi Eric,

 

Can you elaborate on PFR_RST# signal and what is the different between current BMC_RESET# pin 253 ?

BMC_RESET#  also keep BMC in reset (core reset).


BMC_RESET# is to drive "Chip level reset" or "Power-Up Reset".
PFR_RST# is to drive "SOC level reset" or "BMC CPU Reset Input".  
 

 

what is the usage of BMC_PWRGD(output) ? is it from RunBMC to MB signal ?

Note that currently there is PWRGD signal pin 77 from MB to RunBMC.


BMC_PWRGD output is from RunBMC to MB. 
BMC_PWRGD output that would indicate the power on the RunBMC module is good. 
 

 

Can you elaborate on PLT_RST# signal ? is it BMC power-on-reset signal ?


The PLT_RST# signal rename is to better indicate the usage of this signal with no change in original functionality. 
This is "Platform Reset" instead of "CPU Reset".  This signal will monitor CPU/Platform resets. 

In the spec we have this function defined as "Host CPU Reset Monitor" and will change
this to "Host Platform Reset Monitor"
 

Note that Nuvoton model currently support it on pin 95.

 

Regards,

Lior.

 

From: OCP-HWMgt-Module@OCP-All.groups.io <OCP-HWMgt-Module@OCP-All.groups.io> On Behalf Of Eric Shobe via groups.io
Sent: Monday, January 25, 2021 08:02
To: OCP-HWMgt-Module@OCP-All.groups.io
Subject: [OCP-HWMgt-Module] RunBMC v1.5 Change RFC

 


Hi all,

 

I want to welcome everyone to comment on the following proposed changes for RunBMC v1.5. 

The change requests we have received so far are the following:

 

  •  Add Display Port Functionality [need to decide]

 

From RunBMC pins perspective the VGA pins could be reused for Display Port assuming 2 Lanes, Aux Lane and presence detect there are exactly 7 pins needed. 

The following high level changes would be needed to support this. 

 

1. Add filtering for TX pairs 

2. Add HW straps on daughter board to support dual function for TX pairs
3. Add HW straps for AUX diff pair
4. Add HW strap HPD presence
5. Describe filtering/circuitry needed near DP connector on mobo

 

The pinout proposal is here. 

 

  • eMMC functionality [proposed]

If the specification was to be changed to say "eMMC may be added on the RunBMC module", we don't see that as changing anything.  Today, with the specification, anyone who wants to design a RunBMC module can choose to add eMMC or not.

If designs add eMMC over the connector some will loose 4 pairs of I2C pins (I2C10 to I2C13).

  • BMC SD interface. Add SD interface

Screen Shot 2021-01-24 at 9.43.18 PM.png

 

  • Add PWRGB signal. [proposed]

We will add pin95(GPIO63) to be BMC_PWRGD(output)

 

95 BMC_PWRGD_GPIO63  

 

  • Add PFR Reset Signal [proposed]

We will add one more reset input pin on pin93(GPIO61) as PFR_RST#

93 PFR_RST#_GPIO61 

CPLD/circuitry can use the signal to let BMC in reset state.

  • Change pin name from CPU_RST# to PLT_RST# [proposed]
  • I3C [proposed]

Add the I3C3-6 pin definition below. (The I3C 1.0/1.2V signals
need to co-lay with following GF pins.) If user need the I3C 1.0V/1.2V function, please add
a level shift logic IC at MB side.

 

Screen Shot 2021-01-24 at 9.57.28 PM.png

 

Thanks,

Eric


The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton.


Lior Elbaz
 

Hi Eric,

See embedded.

 

From: OCP-HWMgt-Module@OCP-All.groups.io <OCP-HWMgt-Module@OCP-All.groups.io> On Behalf Of Eric Shobe via groups.io
Sent: Monday, January 25, 2021 19:20
To: OCP-HWMgt-Module@OCP-All.groups.io; Jared Mednick <jared.mednick@...>; Jared Mednick <jaredm@...>
Subject: Re: [OCP-HWMgt-Module] RunBMC v1.5 Change RFC

 

 

 

On Mon, Jan 25, 2021 at 7:44 AM Lior Elbaz <lior.albaz@...> wrote:

Hi Eric,

 

Can you elaborate on PFR_RST# signal and what is the different between current BMC_RESET# pin 253 ?

BMC_RESET#  also keep BMC in reset (core reset).

 

BMC_RESET# is to drive "Chip level reset" or "Power-Up Reset".

PFR_RST# is to drive "SOC level reset" or "BMC CPU Reset Input".  

 

Lior> Note that in Nuvoton model we used BMC_RESET# (CPU Reset) pin 253  as "BMC CPU Reset Input" and pin 95 as "Power-Up Reset".

 

 

what is the usage of BMC_PWRGD(output) ? is it from RunBMC to MB signal ?

Note that currently there is PWRGD signal pin 77 from MB to RunBMC.

 

BMC_PWRGD output is from RunBMC to MB. 

BMC_PWRGD output that would indicate the power on the RunBMC module is good. 

 

Lior> so this can be implemented by BMC GPIO that default to low and set high by the FW when BMC is ready. It will indicate FW is running as well.

 

Can you elaborate on PLT_RST# signal ? is it BMC power-on-reset signal ?

 

The PLT_RST# signal rename is to better indicate the usage of this signal with no change in original functionality. 

This is "Platform Reset" instead of "CPU Reset".  This signal will monitor CPU/Platform resets. 

 

In the spec we have this function defined as "Host CPU Reset Monitor" and will change

this to "Host Platform Reset Monitor"

 

Lior> I assume this a new pin assignment regards to V1.0 and not related to pin BMC_RESET#  253.

Note that Nuvoton model currently support it on pin 95.

 

Regards,

Lior.

 

From: OCP-HWMgt-Module@OCP-All.groups.io <OCP-HWMgt-Module@OCP-All.groups.io> On Behalf Of Eric Shobe via groups.io
Sent: Monday, January 25, 2021 08:02
To: OCP-HWMgt-Module@OCP-All.groups.io
Subject: [OCP-HWMgt-Module] RunBMC v1.5 Change RFC

 


Hi all,

 

I want to welcome everyone to comment on the following proposed changes for RunBMC v1.5. 

The change requests we have received so far are the following:

 

  •  Add Display Port Functionality [need to decide]

 

From RunBMC pins perspective the VGA pins could be reused for Display Port assuming 2 Lanes, Aux Lane and presence detect there are exactly 7 pins needed. 

The following high level changes would be needed to support this. 

 

1. Add filtering for TX pairs 

2. Add HW straps on daughter board to support dual function for TX pairs
3. Add HW straps for AUX diff pair
4. Add HW strap HPD presence
5. Describe filtering/circuitry needed near DP connector on mobo

 

The pinout proposal is here. 

 

  • eMMC functionality [proposed]

If the specification was to be changed to say "eMMC may be added on the RunBMC module", we don't see that as changing anything.  Today, with the specification, anyone who wants to design a RunBMC module can choose to add eMMC or not.

If designs add eMMC over the connector some will loose 4 pairs of I2C pins (I2C10 to I2C13).

  • BMC SD interface. Add SD interface

Screen Shot 2021-01-24 at 9.43.18 PM.png

 

  • Add PWRGB signal. [proposed]

We will add pin95(GPIO63) to be BMC_PWRGD(output)

 

95 BMC_PWRGD_GPIO63  

 

  • Add PFR Reset Signal [proposed]

We will add one more reset input pin on pin93(GPIO61) as PFR_RST#

93 PFR_RST#_GPIO61 

CPLD/circuitry can use the signal to let BMC in reset state.

  • Change pin name from CPU_RST# to PLT_RST# [proposed]
  • I3C [proposed]

Add the I3C3-6 pin definition below. (The I3C 1.0/1.2V signals
need to co-lay with following GF pins.) If user need the I3C 1.0V/1.2V function, please add
a level shift logic IC at MB side.

 

Screen Shot 2021-01-24 at 9.57.28 PM.png

 

Thanks,

Eric


The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton.


The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton.


Wszolek, Kasper
 

Hi Eric,

 

Did you consider adding more I3C interfaces than 4 in the pinout proposal below? I think we should try to define more I3C (total 6) even with some limitations defined in the spec for backward compatibility (level shifting on RunBMC module as an example).  

 

--

Thanks,

Kasper

 

 

From: OCP-HWMgt-Module@OCP-All.groups.io <OCP-HWMgt-Module@OCP-All.groups.io> On Behalf Of Lior Elbaz
Sent: Monday, January 25, 2021 19:14
To: OCP-HWMgt-Module@OCP-All.groups.io; Jared Mednick <jared.mednick@...>; Jared Mednick <jaredm@...>
Subject: Re: [OCP-HWMgt-Module] RunBMC v1.5 Change RFC

 

Hi Eric,

See embedded.

 

From: OCP-HWMgt-Module@OCP-All.groups.io <OCP-HWMgt-Module@OCP-All.groups.io> On Behalf Of Eric Shobe via groups.io
Sent: Monday, January 25, 2021 19:20
To: OCP-HWMgt-Module@OCP-All.groups.io; Jared Mednick <jared.mednick@...>; Jared Mednick <jaredm@...>
Subject: Re: [OCP-HWMgt-Module] RunBMC v1.5 Change RFC

 

 

 

On Mon, Jan 25, 2021 at 7:44 AM Lior Elbaz <lior.albaz@...> wrote:

Hi Eric,

 

Can you elaborate on PFR_RST# signal and what is the different between current BMC_RESET# pin 253 ?

BMC_RESET#  also keep BMC in reset (core reset).

 

BMC_RESET# is to drive "Chip level reset" or "Power-Up Reset".

PFR_RST# is to drive "SOC level reset" or "BMC CPU Reset Input".  

 

Lior> Note that in Nuvoton model we used BMC_RESET# (CPU Reset) pin 253  as "BMC CPU Reset Input" and pin 95 as "Power-Up Reset".

 

 

what is the usage of BMC_PWRGD(output) ? is it from RunBMC to MB signal ?

Note that currently there is PWRGD signal pin 77 from MB to RunBMC.

 

BMC_PWRGD output is from RunBMC to MB. 

BMC_PWRGD output that would indicate the power on the RunBMC module is good. 

 

Lior> so this can be implemented by BMC GPIO that default to low and set high by the FW when BMC is ready. It will indicate FW is running as well.

 

Can you elaborate on PLT_RST# signal ? is it BMC power-on-reset signal ?

 

The PLT_RST# signal rename is to better indicate the usage of this signal with no change in original functionality. 

This is "Platform Reset" instead of "CPU Reset".  This signal will monitor CPU/Platform resets. 

 

In the spec we have this function defined as "Host CPU Reset Monitor" and will change

this to "Host Platform Reset Monitor"

 

Lior> I assume this a new pin assignment regards to V1.0 and not related to pin BMC_RESET#  253.

Note that Nuvoton model currently support it on pin 95.

 

Regards,

Lior.

 

From: OCP-HWMgt-Module@OCP-All.groups.io <OCP-HWMgt-Module@OCP-All.groups.io> On Behalf Of Eric Shobe via groups.io
Sent: Monday, January 25, 2021 08:02
To: OCP-HWMgt-Module@OCP-All.groups.io
Subject: [OCP-HWMgt-Module] RunBMC v1.5 Change RFC

 


Hi all,

 

I want to welcome everyone to comment on the following proposed changes for RunBMC v1.5. 

The change requests we have received so far are the following:

 

  •  Add Display Port Functionality [need to decide]

 

From RunBMC pins perspective the VGA pins could be reused for Display Port assuming 2 Lanes, Aux Lane and presence detect there are exactly 7 pins needed. 

The following high level changes would be needed to support this. 

 

1. Add filtering for TX pairs 

2. Add HW straps on daughter board to support dual function for TX pairs
3. Add HW straps for AUX diff pair
4. Add HW strap HPD presence
5. Describe filtering/circuitry needed near DP connector on mobo

 

The pinout proposal is here. 

 

  • eMMC functionality [proposed]

If the specification was to be changed to say "eMMC may be added on the RunBMC module", we don't see that as changing anything.  Today, with the specification, anyone who wants to design a RunBMC module can choose to add eMMC or not.

If designs add eMMC over the connector some will loose 4 pairs of I2C pins (I2C10 to I2C13).

  • BMC SD interface. Add SD interface

Screen Shot 2021-01-24 at 9.43.18 PM.png

 

  • Add PWRGB signal. [proposed]

We will add pin95(GPIO63) to be BMC_PWRGD(output)

 

95 BMC_PWRGD_GPIO63  

 

  • Add PFR Reset Signal [proposed]

We will add one more reset input pin on pin93(GPIO61) as PFR_RST#

93 PFR_RST#_GPIO61 

CPLD/circuitry can use the signal to let BMC in reset state.

  • Change pin name from CPU_RST# to PLT_RST# [proposed]
  • I3C [proposed]

Add the I3C3-6 pin definition below. (The I3C 1.0/1.2V signals
need to co-lay with following GF pins.) If user need the I3C 1.0V/1.2V function, please add
a level shift logic IC at MB side.

 

Screen Shot 2021-01-24 at 9.57.28 PM.png

 

Thanks,

Eric


The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton.


The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton.

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Eric Shobe
 

+Jared Mednick - I've been sort of waiting for the DC-SCM spec to see what happens there. 
What is driving the need of 6 if I may ask?
Eric

On Fri, Feb 5, 2021 at 10:54 AM Wszolek, Kasper <kasper.wszolek@...> wrote:

Hi Eric,

 

Did you consider adding more I3C interfaces than 4 in the pinout proposal below? I think we should try to define more I3C (total 6) even with some limitations defined in the spec for backward compatibility (level shifting on RunBMC module as an example).  

 

--

Thanks,

Kasper

 

 

From: OCP-HWMgt-Module@OCP-All.groups.io <OCP-HWMgt-Module@OCP-All.groups.io> On Behalf Of Lior Elbaz
Sent: Monday, January 25, 2021 19:14
To: OCP-HWMgt-Module@OCP-All.groups.io; Jared Mednick <jared.mednick@...>; Jared Mednick <jaredm@...>
Subject: Re: [OCP-HWMgt-Module] RunBMC v1.5 Change RFC

 

Hi Eric,

See embedded.

 

From: OCP-HWMgt-Module@OCP-All.groups.io <OCP-HWMgt-Module@OCP-All.groups.io> On Behalf Of Eric Shobe via groups.io
Sent: Monday, January 25, 2021 19:20
To: OCP-HWMgt-Module@OCP-All.groups.io; Jared Mednick <jared.mednick@...>; Jared Mednick <jaredm@...>
Subject: Re: [OCP-HWMgt-Module] RunBMC v1.5 Change RFC

 

 

 

On Mon, Jan 25, 2021 at 7:44 AM Lior Elbaz <lior.albaz@...> wrote:

Hi Eric,

 

Can you elaborate on PFR_RST# signal and what is the different between current BMC_RESET# pin 253 ?

BMC_RESET#  also keep BMC in reset (core reset).

 

BMC_RESET# is to drive "Chip level reset" or "Power-Up Reset".

PFR_RST# is to drive "SOC level reset" or "BMC CPU Reset Input".  

 

Lior> Note that in Nuvoton model we used BMC_RESET# (CPU Reset) pin 253  as "BMC CPU Reset Input" and pin 95 as "Power-Up Reset".

 

 

what is the usage of BMC_PWRGD(output) ? is it from RunBMC to MB signal ?

Note that currently there is PWRGD signal pin 77 from MB to RunBMC.

 

BMC_PWRGD output is from RunBMC to MB. 

BMC_PWRGD output that would indicate the power on the RunBMC module is good. 

 

Lior> so this can be implemented by BMC GPIO that default to low and set high by the FW when BMC is ready. It will indicate FW is running as well.

 

Can you elaborate on PLT_RST# signal ? is it BMC power-on-reset signal ?

 

The PLT_RST# signal rename is to better indicate the usage of this signal with no change in original functionality. 

This is "Platform Reset" instead of "CPU Reset".  This signal will monitor CPU/Platform resets. 

 

In the spec we have this function defined as "Host CPU Reset Monitor" and will change

this to "Host Platform Reset Monitor"

 

Lior> I assume this a new pin assignment regards to V1.0 and not related to pin BMC_RESET#  253.

Note that Nuvoton model currently support it on pin 95.

 

Regards,

Lior.

 

From: OCP-HWMgt-Module@OCP-All.groups.io <OCP-HWMgt-Module@OCP-All.groups.io> On Behalf Of Eric Shobe via groups.io
Sent: Monday, January 25, 2021 08:02
To: OCP-HWMgt-Module@OCP-All.groups.io
Subject: [OCP-HWMgt-Module] RunBMC v1.5 Change RFC

 


Hi all,

 

I want to welcome everyone to comment on the following proposed changes for RunBMC v1.5. 

The change requests we have received so far are the following:

 

  •  Add Display Port Functionality [need to decide]

 

From RunBMC pins perspective the VGA pins could be reused for Display Port assuming 2 Lanes, Aux Lane and presence detect there are exactly 7 pins needed. 

The following high level changes would be needed to support this. 

 

1. Add filtering for TX pairs 

2. Add HW straps on daughter board to support dual function for TX pairs
3. Add HW straps for AUX diff pair
4. Add HW strap HPD presence
5. Describe filtering/circuitry needed near DP connector on mobo

 

The pinout proposal is here. 

 

  • eMMC functionality [proposed]

If the specification was to be changed to say "eMMC may be added on the RunBMC module", we don't see that as changing anything.  Today, with the specification, anyone who wants to design a RunBMC module can choose to add eMMC or not.

If designs add eMMC over the connector some will loose 4 pairs of I2C pins (I2C10 to I2C13).

  • BMC SD interface. Add SD interface

Screen Shot 2021-01-24 at 9.43.18 PM.png

 

  • Add PWRGB signal. [proposed]

We will add pin95(GPIO63) to be BMC_PWRGD(output)

 

95 BMC_PWRGD_GPIO63  

 

  • Add PFR Reset Signal [proposed]

We will add one more reset input pin on pin93(GPIO61) as PFR_RST#

93 PFR_RST#_GPIO61 

CPLD/circuitry can use the signal to let BMC in reset state.

  • Change pin name from CPU_RST# to PLT_RST# [proposed]
  • I3C [proposed]

Add the I3C3-6 pin definition below. (The I3C 1.0/1.2V signals
need to co-lay with following GF pins.) If user need the I3C 1.0V/1.2V function, please add
a level shift logic IC at MB side.

 

Screen Shot 2021-01-24 at 9.57.28 PM.png

 

Thanks,

Eric


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The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton.

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Wszolek, Kasper
 

Hi Eric,

 

For current DC-SCM 2.0 pinout we settled at 6 x I3C minimum and 8 x I2C/I3C 1.8V that will allow to easily move from I2C to I3C in the future without pinout change. The DC-SCM 2.0 decision is driven by expectation that more use cases will be moving from I2C/SMBus to I3C and we’ll be able to utilize all BMC links available + more in the future.

 

--

Thanks,

Kasper

 

From: OCP-HWMgt-Module@OCP-All.groups.io <OCP-HWMgt-Module@OCP-All.groups.io> On Behalf Of Eric Shobe
Sent: Wednesday, March 10, 2021 06:55
To: OCP-HWMgt-Module@OCP-All.groups.io
Cc: Jared Mednick <jared.mednick@...>; Jared Mednick <jaredm@...>
Subject: Re: [OCP-HWMgt-Module] RunBMC v1.5 Change RFC

 

+Jared Mednick - I've been sort of waiting for the DC-SCM spec to see what happens there. 
What is driving the need of 6 if I may ask?

Eric

 

On Fri, Feb 5, 2021 at 10:54 AM Wszolek, Kasper <kasper.wszolek@...> wrote:

Hi Eric,

 

Did you consider adding more I3C interfaces than 4 in the pinout proposal below? I think we should try to define more I3C (total 6) even with some limitations defined in the spec for backward compatibility (level shifting on RunBMC module as an example).  

 

--

Thanks,

Kasper

 

 

From: OCP-HWMgt-Module@OCP-All.groups.io <OCP-HWMgt-Module@OCP-All.groups.io> On Behalf Of Lior Elbaz
Sent: Monday, January 25, 2021 19:14
To: OCP-HWMgt-Module@OCP-All.groups.io; Jared Mednick <jared.mednick@...>; Jared Mednick <jaredm@...>
Subject: Re: [OCP-HWMgt-Module] RunBMC v1.5 Change RFC

 

Hi Eric,

See embedded.

 

From: OCP-HWMgt-Module@OCP-All.groups.io <OCP-HWMgt-Module@OCP-All.groups.io> On Behalf Of Eric Shobe via groups.io
Sent: Monday, January 25, 2021 19:20
To: OCP-HWMgt-Module@OCP-All.groups.io; Jared Mednick <jared.mednick@...>; Jared Mednick <jaredm@...>
Subject: Re: [OCP-HWMgt-Module] RunBMC v1.5 Change RFC

 

 

 

On Mon, Jan 25, 2021 at 7:44 AM Lior Elbaz <lior.albaz@...> wrote:

Hi Eric,

 

Can you elaborate on PFR_RST# signal and what is the different between current BMC_RESET# pin 253 ?

BMC_RESET#  also keep BMC in reset (core reset).

 

BMC_RESET# is to drive "Chip level reset" or "Power-Up Reset".

PFR_RST# is to drive "SOC level reset" or "BMC CPU Reset Input".  

 

Lior> Note that in Nuvoton model we used BMC_RESET# (CPU Reset) pin 253  as "BMC CPU Reset Input" and pin 95 as "Power-Up Reset".

 

 

what is the usage of BMC_PWRGD(output) ? is it from RunBMC to MB signal ?

Note that currently there is PWRGD signal pin 77 from MB to RunBMC.

 

BMC_PWRGD output is from RunBMC to MB. 

BMC_PWRGD output that would indicate the power on the RunBMC module is good. 

 

Lior> so this can be implemented by BMC GPIO that default to low and set high by the FW when BMC is ready. It will indicate FW is running as well.

 

Can you elaborate on PLT_RST# signal ? is it BMC power-on-reset signal ?

 

The PLT_RST# signal rename is to better indicate the usage of this signal with no change in original functionality. 

This is "Platform Reset" instead of "CPU Reset".  This signal will monitor CPU/Platform resets. 

 

In the spec we have this function defined as "Host CPU Reset Monitor" and will change

this to "Host Platform Reset Monitor"

 

Lior> I assume this a new pin assignment regards to V1.0 and not related to pin BMC_RESET#  253.

Note that Nuvoton model currently support it on pin 95.

 

Regards,

Lior.

 

From: OCP-HWMgt-Module@OCP-All.groups.io <OCP-HWMgt-Module@OCP-All.groups.io> On Behalf Of Eric Shobe via groups.io
Sent: Monday, January 25, 2021 08:02
To: OCP-HWMgt-Module@OCP-All.groups.io
Subject: [OCP-HWMgt-Module] RunBMC v1.5 Change RFC

 


Hi all,

 

I want to welcome everyone to comment on the following proposed changes for RunBMC v1.5. 

The change requests we have received so far are the following:

 

  •  Add Display Port Functionality [need to decide]

 

From RunBMC pins perspective the VGA pins could be reused for Display Port assuming 2 Lanes, Aux Lane and presence detect there are exactly 7 pins needed. 

The following high level changes would be needed to support this. 

 

1. Add filtering for TX pairs 

2. Add HW straps on daughter board to support dual function for TX pairs
3. Add HW straps for AUX diff pair
4. Add HW strap HPD presence
5. Describe filtering/circuitry needed near DP connector on mobo

 

The pinout proposal is here. 

 

  • eMMC functionality [proposed]

If the specification was to be changed to say "eMMC may be added on the RunBMC module", we don't see that as changing anything.  Today, with the specification, anyone who wants to design a RunBMC module can choose to add eMMC or not.

If designs add eMMC over the connector some will loose 4 pairs of I2C pins (I2C10 to I2C13).

  • BMC SD interface. Add SD interface

Screen Shot 2021-01-24 at 9.43.18 PM.png

 

  • Add PWRGB signal. [proposed]

We will add pin95(GPIO63) to be BMC_PWRGD(output)

 

95 BMC_PWRGD_GPIO63  

 

  • Add PFR Reset Signal [proposed]

We will add one more reset input pin on pin93(GPIO61) as PFR_RST#

93 PFR_RST#_GPIO61 

CPLD/circuitry can use the signal to let BMC in reset state.

  • Change pin name from CPU_RST# to PLT_RST# [proposed]
  • I3C [proposed]

Add the I3C3-6 pin definition below. (The I3C 1.0/1.2V signals
need to co-lay with following GF pins.) If user need the I3C 1.0V/1.2V function, please add
a level shift logic IC at MB side.

 

Screen Shot 2021-01-24 at 9.57.28 PM.png

 

Thanks,

Eric


The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton.


The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton.

---------------------------------------------------------------------
Intel Technology Poland sp. z o.o.
ul. Słowackiego 173 | 80-298 Gdańsk | Sąd Rejonowy Gdańsk Północ | VII Wydział Gospodarczy Krajowego Rejestru Sądowego - KRS 101882 | NIP 957-07-52-316 | Kapitał zakładowy 200.000 PLN.
Ta wiadomość wraz z załącznikami jest przeznaczona dla określonego adresata i może zawierać informacje poufne. W razie przypadkowego otrzymania tej wiadomości, prosimy o powiadomienie nadawcy oraz trwałe jej usunięcie; jakiekolwiek przeglądanie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by others is strictly prohibited.

---------------------------------------------------------------------
Intel Technology Poland sp. z o.o.
ul. Słowackiego 173 | 80-298 Gdańsk | Sąd Rejonowy Gdańsk Północ | VII Wydział Gospodarczy Krajowego Rejestru Sądowego - KRS 101882 | NIP 957-07-52-316 | Kapitał zakładowy 200.000 PLN.
Ta wiadomość wraz z załącznikami jest przeznaczona dla określonego adresata i może zawierać informacje poufne. W razie przypadkowego otrzymania tej wiadomości, prosimy o powiadomienie nadawcy oraz trwałe jej usunięcie; jakiekolwiek przeglądanie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by others is strictly prohibited.